View ETK6207_7248565.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

ETK6207 rev 1.2 2010-05-14 1/17 etek microelectronics led control driver general description ETK6207 is an led control driver on a 1/7 to 1/8 duty factor. 6 segment output lines, 4 grid output lines, 3 segment/grid output lines, one display memory, control circuit, key scan circuit are all incorporated into a single chip to build a highly reliable peripheral device for a single chip microcomputer. serial data is fed to ETK6207 via a three-line serial interface. features z cmos technology z low power consumption z multiple display modes(4 7 grid , 6 9segment) z key scaning(61 matrix) z 8-step dimming circuitry z serial interface for clock, data input, data output, strobe pins z package: tssop20(ETK6207) pin configuration 2 3 4 5 6 7 8 1 10 9 osc di /o cl k st b k2 vd d sg1 / ks1 sg2 / ks2 sg3 / ks3 sg4 / ks4 sg5 / ks5 sg6 / ks6 sg12/gr7 sg13/gr6 sg14/gr5 gn d gr 1 gr 2 gr 3 gr 4 11 12 13 14 15 16 17 18 19 20 et k62 07 free datasheet http:///
ETK6207 rev 1.2 2010-05-14 2/17 pin function pin no pin name i/o description 1 osc i oscillator input pin a resistor is connected to this pin to determine the oscillation frequency 2 di/o data output and input pin(n-channel, open-drain) this pin outputs serial data at the falling edge of the shift clock and that pin inputs serial data at the rising edge of the shift clock. 3 clk i clock input pin this pin reads serial data at the rising edge and outputs data at the falling edge 4 stb i serial interface strobe pin the data input after the stb has fallen is processed as a command when this pin is ?high?, clk is ignored 5 k2 i key data input pins the data sent to these pins are latched at the end of the display cycle (interface pull-low resistor) 6 vdd power supply 712 sg1/ks1 sg6/ks6 o segment output pins(p-channel, open drain) also acts as the key source 13 15 sg12/gr7 sg14/gr5 o segment/grid output pins 18 gnd grond pin 16 17 1920 gr4 gr1 o grid output pins input/output configurations the schematic diagrams of the input and output circuits of the logic section are shown below. 1. input pins clk stb&di/o gnd free datasheet http:///
ETK6207 rev 1.2 2010-05-14 3/17 2. input pins k2 vd d gnd 3. output pins di/o gr1 gr4 vd d gnd 4. output pins sg1 sg6 vd d gnd free datasheet http:///
ETK6207 rev 1.2 2010-05-14 4/17 5. sg12/gr7 sg14/gr5 vd d gnd block diagram r osc gnd sg1/ks1 sg2/ks2 sg3/ks3 sg4/ks4 sg5/ks5 sg6/ks6 sg12/gr7 gr 1 gr 2 gr 3 gr 4 sg14/gr5 sg13/gr6 di/o clk stb k2 vdd gnd serial data interface osc control display memory timing generator key matrix me mory diming circuit segment driver key sca n output grid driver free datasheet http:///
ETK6207 rev 1.2 2010-05-14 5/17 functional description commands a command is the first byte(b0 b7) inputted to ETK6207 via the din pin after stb pin has changed from high to low state. if for some reason the stb pin is set to high while data or commands are being transmitted, the serial communication is initialized, and the data/commands being transmitted are considered invalid. command 1 display mode setting commands ETK6207 provides 2 display mode settings as shown in the diagram below as started earlier a command is the first one byte(b0 b7) transmitted to ETK6207 via the din pin when stb is low. however, for these commands, the bit 3 to bit 6(b2 b5)are ignored, bit 7&bit 8(b6 b7) are given a value of 0. the display mode setting commands determine the number of segments and grids to be used (6 to 9 segments, 4 to 7 grids). a display commands on must be executed in order to resume display. if the same mode setting is selected, no command execution is take place, therefore, nothing happens. when power is turned on, the 7-grid, 6-segment modes is selected. msb lsb 0 0 b1 b0 b2 b5: not relevant display mode setting b1, b0?0 0: 4 grids, 9 segments b1, b0?0 1: 5 grids, 8 segments b1, b0?1 0: 6 grids, 7 segments b1, b0?1 1: 7 grids, 6 segments command 2: data setting commands data setting commands executes the data write or data r ead modes for ETK6207. the data setting command, the bits 5 and 6(b4, b5) are ignored, bit 7(b6) is given th e value of 1 while bit 8(b7) is given the value of 0. when power is turned on, bit 4 to bit 1(b3 b0) are given the value of 0 msb lsb 0 1 b3 b2 b1 b0 b4,b5 not relevant mode setting b3 ?0 normal operation mode b3?1 test mode address increment mode settings(display mode) b2?0 increment address after data has been written b2?1 fixes address data write & read mode setting b1,b0?0 0 write data to display mode b1,b0?1 0 read key data free datasheet http:///
ETK6207 rev 1.2 2010-05-14 6/17 ETK6207 key matrix&key input data storage ram ETK6207 key matrix consists of 61 array as shown below k2 sg1/ sg2/ sg3/ sg4/ sg5/ sg6/ ks1 ks2 ks3 ks4 ks5 ks6 each data entered by each key is stored as follows and read by a read command, starting from the last significant bit of the next data(b7) is read. k2 k2 sg1/ks1 sg2/ks2 x sg3/ks3 sg4/ks4 x sg5/ks5 sg6/ks6 x reading sequence b1 b4 b7 note b7 do not care. command 3 address setting commands address setting commands are used to se t the address of the display memory. the address is considered valid if it has a value of 00h to 0dh. if the address is set to 0eh or higher, the data is ignored until a valid address is set. when power is turned on, the address is set at 00h. msb lsb 1 1 b3 b2 b1 b0 b4, b5: not relevant the address of b3 b0: 00h 0dh free datasheet http:///
ETK6207 rev 1.2 2010-05-14 7/17 display mode and ram address data transmitted from an external device to ETK6207 vi a the interface are stored in the display ram and are assigned address. the ram addresses of ETK6207 are given below in 8 bits unit. sg1????sg4 sg5????sg8 sg9????sg12 sg13????sg16 00h l 00h u 01h l 01h u dig1 02h l 02h u 03h l 03h u dig2 04h l 04h u 05h l 05h u dig3 06h l 06h u 07h l 07h u dig4 08h l 08h u 09h l 09h u dig5 0ah l 0ah u 0bh l 0bh u dig6 0ch l 0ch u 0dh l 0dh u dig7 b0?????.b3 b4??????b7 xxh l xxh u lower 4 bits higher 4 bits command 4 display control commands the display control commands are used to turn on or off a display. it also used to set the pulse width. please refer to the diagram below. when the power is turn ed on, a 1/16 pulse width is selected and the displayed is turned off (the key scanning is stopped). msb lsb 1 0 b3 b2 b1 b0 b4, b5 not relevant display setting b3 0 display off (key scan continues) b3 1 display on dimming quantity setting 000 pulse width=1/16 001 pulse width =2/16 010 pulse width =4/16 011 pulse width =10/16 100 pulse width =11/16 101 pulse width =12/16 110 pulse width =13/16 111 pulse width =14/16 free datasheet http:///
ETK6207 rev 1.2 2010-05-14 8/17 s canning and display timing the key scanning and display timing diagram is given below. one cycle of key scanning consists of 2 frames. the data of the 61 matrix is stored in the ram. sg output dig1 dig2 dig3 dign dig1 1 frame=tdisplay n+1 g1 g2 g3 gn tdisplay=500us key scan data free datasheet http:///
ETK6207 rev 1.2 2010-05-14 9/17 serial communication format the following diagram shows the ETK6207 serial communi cation format. the di/o pin is an n-channel, open-drain output pin, therefore, it is highly r ecommended that an external pull-up resistor(1k 10k) must be connected to di/o. if dat a cont inues st b din 123 78 b0 b1 b2 b6 b7 clk reception(data/command write) stb din 123 78 b0 b1 b2 b3 clk b4 b5 b6 b7 456 123 456 b0 b1 b2 b3 b4 b5 dout t wait data read command is set data reading starts transmission(data read) t wait (waiting time) 1s it must be noted that when the data is read, the waiting time (t wait ) between the risings of the eighth clock that has set the command and the galling of the first clock that has read the data is greater or equal to 1s. free datasheet http:///
ETK6207 rev 1.2 2010-05-14 10/17 switching characteristic waveform ETK6207 switching characteristics waveform is given below. pw stb t clk- stb fosc 50% t setup t hold t tzl t tlz t tzh t thz 90% 10% 10% 90% osc st b clk di/o gn sn pw clk pw clk pw clk clock pulse width 400ns pw stb strobe pulse width 1s t setup data setup time 100ns t hold data hold time 100ns t clk-stb clock-strobe time 1s t thz fall time 10s t tzh rise time 1s fosc=oscillation frequency t tzl <1s t tlz <10s notetest condition under t thz pull low resistor=10k ? loading capacitor=300pf t tlz pull low resistor=10k ? loading capacitor =300pf free datasheet http:///
ETK6207 rev 1.2 2010-05-14 11/17 application 1. display memory is updated by incrementing addr esses. please refer to the following diagram. c omma nd 1 c omma nd 2 c omma nd 3 c omma nd 4 data 1 data n stb clk din command 1 display mode setting command command 2 data setting command command 3 address setting command data 1 n transfer display data (14 bytes max) command 4 display control command 2. the following diagram shows the waveform when updating specific addresses. command3 comma nd2 comma nd3 da ta data stb clk din command 2 data setting command command 3 address setting command data display data free datasheet http:///
ETK6207 rev 1.2 2010-05-14 12/17 recommended software programming flowchart st art delay 200 ms set command2 (writer data) set command3 clear display ram (see note 5) set command1 set command4 (88h-8fh display on) main program set command2 (read key & writer data included) set command3 set command1 set command4 end initial set ting main loop set command1 set command4 (88h-87h display off) free datasheet http:///
ETK6207 rev 1.2 2010-05-14 13/17 note: 1. command 1: display mode commands 2. command 2: data setting commands 3. command 3: address setting commands 4. command 4: display control commands when ic power is applied for the first time, the content of the display ram is not defined; thus, it is strongly suggested that the contents of the display ram must be cleared during the initial setting. absolute maximum ratings 1. ta=25 ,gnd=0v parameter symbol ratings unit supply voltage v dd -0.5 +7 v logic input voltage v i -0.5 v dd +0.5 v i olgr +250 ma driver output current i ohsg -50 ma maximum driver output current/total i total 400 ma 2. recommended operating range ta= -20 +70 ,gnd=0v parameter symbol min. typ. max. unit logic supply voltage v dd 3 5 5.5 v dynamic current(see note) i dddyn 5 ma high-level input voltage v ih 0.6v dd v dd v low- level input voltage v il 0 0.3v dd v note test condition set display control commands=80h (display turn off state & under no load) free datasheet http:///
ETK6207 rev 1.2 2010-05-14 14/17 electrical characteristics v dd =5v, gnd=0v, ta=25 parameter symbol test condition min. typ. max. unit i ohsg1 v o = v dd -2v sg1 sg6, sg12 sg14 -20 -25 -40 ma high-level output current i ohsg2 v o = v dd -3v sg1 sg6, sg12 sg14 -25 -30 -50 ma low-level output current i olgr v o =0.3v gr1 gr7, 100 140 ma low-level output current i oldout v o =0.4v 4 ma segment high-level output current tolerance i tolsg v o = v dd -3v sg1 sg6, sg12 sg14 +5 % high-level input voltage v ih 0.6v dd 5 v low-level input voltage v il 0 0.3v dd v oscillation frequency fosc r=51k 350 500 650 khz k2 pull down resistor r kn k2 v dd =5v 40 100 k ? free datasheet http:///
ETK6207 rev 1.2 2010-05-14 15/17 v dd =3v, gnd=0v, ta=25 parameter symbol test condition min. typ. max. unit high-level output current i ohsg1 v o = v dd -2v sg1 sg6, sg12 sg14 -15 -20 -35 ma low-level output current i olgr v o =0.3v gr1 gr7, 100 140 ma low-level output current i oldout v o =0.4v 4 ma segment high-level output current tolerance i tolsg v o = v dd -3v sg1 sg6, sg12 sg14 +5 % high-level input voltage v ih 0.8v dd 3.3 v low-level input voltage v il 0 0.3v dd v oscillation frequency fosc r=51k 300 420 580 khz k2 pull down resistor r kn k2 v dd =3v 40 100 k ? free datasheet http:///
ETK6207 rev 1.2 2010-05-14 16/17 application circuits osc di/o clk stb k2 vdd sg1/ks1 sg2/ks2 sg3/ks3 sg4/ks4 sg5/ks5 sg6/ks6 sg12/gr7 sg13/gr6 sg14/gr5 gnd gr1 gr2 gr3 gr4 51k digit1 digit2 digit3 digit4 seg1 seg2 seg3 seg4 seg5 seg6 seg12 seg13 seg14 mcu 3.3k sw6 sw5 sw4 sw3 sw2 sw1 s1 s2 s3 s4 s8 s9 s10 s11 s12 g1 g2 g3 g4 g1 g2 g3 g4 s1 s2 s3 s4 s5 s6 s12 s13 s14 ks1 ks2 ks3 ks4 ks5 ks6 +5 +5 3.3k 3.3k 6segment7grid common cathode note 1. the capacitor (0.1f) connected between the gnd and vdd pins must be located as close as possible to the ETK6207 chip. 2. it is strongly suggested that the nc pin (pins 10) be connected to the gnd. free datasheet http:///
ETK6207 rev 1.2 2010-05-14 17/17 package dimension tssop20 0.65 4.400.10 6.400.20 6.450.10 1.20max 0.600.15 uni t mm 0.10 0 8 0.90 1.05 0.05 0.15 0.20 0.28 note: level 1 environment-related substances in ss-00259 should never be used. purchase ink, paint, wire rods, and molding resins only from the business partner that sony approves as green partners. free datasheet http:///

▲Up To Search▲

Price & Availability of ETK6207

	To Download ETK6207 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .